Synopsys builds 3D into tool portfolio
At the SNUG event this week, Synopsys is taking the wraps off its plans to support 3DIC, an area that is seeing a lot more public activity this month after Altera's announcement of plans for work on...
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3D-IC integration prospects improving, say IEDM researchers
It looks like the performance impact of building systems using 3D-IC integration techniques (Guide) such as thinned wafers and through-silicon vias will be limited, according to two presentations at...
View ArticleDATE: Dark clouds gather over 3D integration, panelist tells conference
The chip industry could face problems as the foundry business and the packaging industry struggle for control of 3D integration technologies, Naveed Sherwani, president of Open-Silicon, told the DATE...
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Amkor keeps question mark next to ‘full’ 3D-IC in 2016
3D-IC projects today are on yields of at best between 95% and 96%, according to leading packaging player Amkor Technology. The market is looking - as it always does - for 'three nines'. Dr Choon-Heung...
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TSMC demonstrates readiness for 3D-IC
One of the more interesting things about 3D-IC is how much of it is about scaling up - about as counter-intuitive a phrase as you can get in silicon design. Though obvious when you think about what we...
View ArticleIntel and Altera extend foundry deal into interposer and full 3D
Altera has extended its foundry agreement with Intel to cover future 3D-IC development, effectively quashing rumors that it was about to move its most advanced production back to TSMC. Intel originally...
View ArticleLeti releases photonics design kit for Synopsys PhoeniX OptoDesigner suite
Leti has released an opto-electronics process design kit (PDK) that includes design rules and building blocks for the research institute's integrated silicon photonics platform. The PDK works with...
View ArticleSynopsys builds 3D into tool portfolio
At the SNUG event this week, Synopsys is taking the wraps off its plans to support 3DIC, an area that is seeing a lot more public activity this month after Altera’s announcement of plans for work on...
View ArticleClik here to view.
3D-IC integration prospects improving, say IEDM researchers
It looks like the performance impact of building systems using 3D-IC integration techniques (Guide) such as thinned wafers and through-silicon vias will be limited, according to two presentations at...
View ArticleDATE: Dark clouds gather over 3D integration, panelist tells conference
The chip industry could face problems as the foundry business and the packaging industry struggle for control of 3D integration technologies, Naveed Sherwani, president of Open-Silicon, told the DATE...
View ArticleClik here to view.
Amkor keeps question mark next to ‘full’ 3D-IC in 2016
3D-IC projects today are on yields of at best between 95% and 96%, according to leading packaging player Amkor Technology. The market is looking – as it always does – for ‘three nines’. Dr Choon-Heung...
View ArticleClik here to view.
TSMC demonstrates readiness for 3D-IC
One of the more interesting things about 3D-IC is how much of it is about scaling up – about as counter-intuitive a phrase as you can get in silicon design. Though obvious when you think about what we...
View ArticleIntel and Altera extend foundry deal into interposer and full 3D
Altera has extended its foundry agreement with Intel to cover future 3D-IC development, effectively quashing rumors that it was about to move its most advanced production back to TSMC. Intel originally...
View ArticleLeti releases photonics design kit for Synopsys PhoeniX OptoDesigner suite
Leti has released an opto-electronics process design kit (PDK) that includes design rules and building blocks for the research institute’s integrated silicon photonics platform. The PDK works with...
View ArticleClik here to view.
Scaling costs tip balance toward chiplets for AMD server processors
Although several of the sessions at the VLSI Symposia showed how CMOS scaling is continuing, the traditionally wise decision to opt for monolithic integration rather than multichip packaging is getting...
View ArticleChoose the right advanced packaging methodology for metal fill rules
Advanced packaging design comes with a wide of foundry and OSAT requirements. A new white paper describes three strategies that can be used to satisfy these needs while also ensuring that the...
View ArticleHow digital twin evaluations optimize STCO-based design
System Technology Co-optimization (STCO) is one of the hot topics in electronics design. In broad terms, it is about the partitioning of an SoC into chiplets that can be designed in parallel or taken...
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Capturing connectivity for assembly verification in 2.5D and 3D design
Successful 2.5D and 3D system development is tricky. A new technical article addresses one of the more challenging aspects: How can you capture assembly connectivity needed for assembly verification...
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Siemens automates test to handle multi-die 2.5D, 3D and 5.5D architectures
Siemens has introduced Tessent Multi-die, design-for-test (DFT) software that targets the particular challenges posed by emerging and increasingly mainstream silicon architectures and structures....
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Chipletz pushes packaging design for AI, HPC and immersive use-cases
Austin-based start-up Chipletz has completed its first design of a Smart Substrate that aims to help deliver the increasing performance needed for artificial intelligence (AI), high-performance...
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